The core of a modern high-speed microprocessor system, as shown in FIG. 1, includes a number of subsystems such as the-microprocessor (CPU 11 ), secondary cache controller 12 and secondary cache memory 13. The communication between the subsystems is performed over the CPU bus 14. Highly integrated modern VLSI processes allow CPU 11 to include an on-chip primary cache 15 and floating point unit (FPU)16. Generally, CPU 11 may include additional units that are not essential to the subject matter of this invention and are therefore omitted for clarity from FIG. 1.
Synchronous operation of the various units in the microprocessor system is accomplished by means of the clock (CLK) signal. Each unit uses the CLK signal for sequencing the operation of internal sequential logic circuits such as synchronous state machines. Inside CPU 11, CLK is generated by the clock generator circuit (CLKGEN) 17. In the past, a double frequency clock, CLK2, was used as a main system reference clock. CLK 2 consisted of a series of pulses occurring at twice the rate of the on-chip CLK.
(In the following description, commonly used clock rate nomenclature such as (1/2)X, 1X, and 2X will be used to indicate the clock period relative to the reference clock (1X). Hence, a (1/2)X clock will have twice the rate of the 1X clock and a 2X clock will have half the rate of the 1X clock.)
FIG. 2 shows a typical prior art implementation of the CLKGEN circuit 17. The frequency of the external CLK2 signal is divided by two using a D-type flip-flop (DFF) 18 with its Q# output connected to its D input. Clock driver (CLKDRV) 19 provides a buffered output CLK with a 50% duty cycle, independent of the duty cycle of CLK 2.
At the higher clock rates of modern microprocessors (50 to 100 MHz), the distribution of a CLK 2 signal with a 100 to 200 MHz rate presents difficult design problems due to the complexity that requires substantial skills in high frequency analog techniques. Also, simple circuits, such as CLKDRV 19, have delays of 2 to 3 ns which are significant when compared with the periods of 50 to 100 MHz clocks. The use of 1X external clock is precluded by the need to generate a 50% duty cycle on-chip clock. In fact, it would be preferable to use an external clock with a one-half rate (2X) for reduced distribution problems if a 1X clock signal with a 50% duty cycle could be readily generated on-chip.
Phase-locked-loop (PLL) circuits have been employed to multiply clock rates for producing 50% duty cycle clock waveforms. Two problems are encountered with the PLL approach: analog circuits are required; and long lock-on times are required for synchronization.
Analog circuits, when included on the same substrate as digital circuits, encounter severe noise problems due to digital "switching" of signals. Also, because of the higher supply voltage (Vcc) required for analog CMOS circuitry, PLL implementation in modern low voltage (1.5 V) CMOS0, (complementary initial-oxide semiconductor) would be manufacturing process incompatible.
FIG. 3 shows a typical prior-art PLL clock generator for producing a CLK signal with 50% duty cycle and 1X rate. The use of a sequential phase-frequency detector (PFD 20) and charge-pump (CP 21) as elements in the PLL results in zero skew between CLK and CLKZ*I. Low-pass filter (LPF 22) smoothes the output of CP 21 before applying the control signal to VCO 23. The 50% duty cycle obtains by using the voltage controlled oscillator (VCO 23) oscillating at twice the CLKEFI frequency and then dividing the clock rate by two using frequency divider network 24. The output of divider network 24 (CLK) is applied to PFD 20 via CLKDRV 25 for comparison with CLKEFI.
A delay line loop (DLL) on-chip clock circuit has been implemented using CMOS circuitry and is described by Waizman in U.S. Pat. No. 5,31 7,202 for "A Delay Line Loop for 1X On-Chip Clock Generation with Zero Skew and 50% Duty Cycle." The DLL is a digital circuit implementation that eliminates the analog circuitry of the PLL. However, because of the closed loop control used in both the DLL and PLL method, long stabilization times are required for resynchronization.
FIG. 4 is a simplified block diagram of a 1X, 50% duty cycle DLL clock generator comprising a CLK waveform generator loop 204 and a delay line (DL) control loop 30. The DL control loop 30 controls the delay elements in the inverting voltage control delay line (IVCDL 32) to ensure a delay of one-half the period of CLKEFI by comparing the output (CLK) with CLKEFI. CLK waveform generator loop 31 operates by using the onset of CLKEFI to form the leading edge of the CLK waveform in waveform generator 34 which is applied to IVCDL 32. One-half period later, the inverted onset of CLK appears at the output of IVCDL 32 as the half-period transition of CLK which is feedback to waveform generator 300 for synthesizing the second half of the CLK period waveform. The necessary filters in both feedback loops result in long settling time when resynchronization is required.